The present invention generally relates to electronic design automation (EDA) tools, and more particularly to an EDA tool for verifying timing constraints of an integrated circuit (IC) design.
Integrated circuits (ICs) including system-on-chips (SoCs) integrate various digital and sometimes analog elements on a single chip. With advancements in semiconductor technology, the operational speed of ICs is increasing and more and more functions are being added to the ICs by increasing the number of circuit elements. This has led to an increase in the complexity of the ICs, thereby leading to a decrease in the yield of the ICs. Thus, testing and verifying a design during the design stage has become increasingly important.
Testing and verification are performed by an EDA tool. In the front-end design stage, the operation of the IC design is described using a hardware description language (HDL) such as Verilog and very high speed integrated circuit (VHSIC) hardware description language (VHDL), and a register transfer level (RTL) file or RTL code is generated that is representative of the IC design. The RTL code is synthesized by the EDA tool to generate a corresponding gate level netlist that is indicative of the IC design and describes the operation of the IC design at the gate level using circuit elements such as logic cells, buffer cells, and clock delay cells from a technology library and interconnections among the circuit elements.
After generation of the netlist, placement, clock tree synthesis, and routing operations are performed. Placement is the process of assigning non-overlapping areas of the netlist to the circuit elements to reduce the area and power requirements of the netlist. Usually the circuit elements that frequently communicate with each other are placed in close proximity in order to reduce the delay of signals and power required during signal transmission.
Clock tree synthesis is the process of inserting clock delay cells in the netlist for meeting clock skew, area, and power constraints. Routing is the process of connecting the circuit elements of the netlist. A delay calculator calculates the delay of signal paths based on a timing library. The signal paths include both clock and data paths. The timing library includes information such as circuit element delay values, interconnecting wires delay values (net delays), and circuit element setup and hold times. Typically, the delay values of the circuit elements and the net delays are estimated delay values.
The netlist also includes non-critical signal paths, which are signal paths that generally are well within timing parameters. Examples of such signal paths include false paths, multi-cycle paths, and signal paths that include circuit elements for receiving asynchronous clock signals, i.e., a signal path between asynchronous clock paths. An example of a false path is a signal path in which changes in an input signal to a source circuit element of the signal path do not affect an output signal of a destination circuit element of the signal path. A multi-cycle path is a signal path that requires more than one clock cycle for transmission of a signal therethrough. A signal path between asynchronous clock paths is a non-critical path because the netlist includes a synchronizer for synchronizing the operations of the circuit elements of the signal path. If data regarding the non-critical signal paths is not provided to the EDA tool for performing a static timing analysis (STA) of the netlist, the EDA tool analyzes the non-critical paths, which increases the time required for verifying the IC design.
During the design stage, designers provide timing constraints required to test the netlist by way of a timing constraint file. The timing constraints corresponding to false paths, multi-cycle paths, and signal paths between asynchronous clock paths are known as false path constraints, multi-cycle path constraints, and asynchronous clock path constraints, respectively. The timing constraint file includes information indicative of the timing constraints such as asynchronous clock, false path, and multi-cycle path constraints. A standard delay format (SDF) file is generated based on a timing constraint file and the delay information using the EDA tool. The SDF file includes timing information such as the delay values of the circuit elements, the net delays, the timing constraints, the setup and hold times of the circuit elements, and the delay values of the signal paths. The SDF file also includes timing information that describes minimum, typical, and maximum delay values of the circuit elements and the interconnecting wires.
Gate level simulation (GLS) is performed by the EDA tool for determining whether the netlist meets the timing requirements based on the SDF file. Based on the GLS, the different steps of the IC design process may be re-performed to meet various requirements such as area, timing, and power requirements.
As the delay values of the circuit elements and the net delays are estimated values, the delay values of the signal paths calculated by the delay calculator also are estimated values. Only one delay value among minimum, typical, and maximum delay values for each circuit element and each interconnecting wire can be used for the GLS, which restricts the use of GLS to limited delay values or delay configurations.
Further, ICs experience on-chip variations, which are introduced due to process, voltage, and temperature variations. Examples of process variations include variation in doping level of a substrate, variation in the length and widths of the circuit elements and the interconnecting wires, and clock crosstalk. Due to the on-chip variations, the delay values of the circuit elements and the interconnecting wires vary. The SDF file does not include timing margins in the delay values of the circuit elements and interconnecting wires. As timing constraints in the timing constraint file are provided by the IC designer, some of the timing constraints may not be valid. Further, GLS is pattern dependent and hence, a transition in a signal may not lie within a setup and hold time margin (hereinafter referred to as “setup and hold time window”) around a clock edge of a clock signal. Thus, a critical signal path propagating the signal may not be verified correctly using the GLS and hence, the timing constraints in the timing constraint file may not be verified. Therefore, the GLS does not ensure that the IC will operate at its desired clock frequency.
STA is performed by the EDA tool for a detailed timing analysis to determine whether the netlist meets the timing requirements based on the SDF. The STA is a topographical analysis of the netlist and does not consider the functionality of the circuit elements and hence depends on the SDF for timing constraints. Thus, in STA, signal paths corresponding to the timing constraints are not analyzed and hence, signal paths corresponding to invalid timing constraints are not verified. Further, STA considers on-chip variations by applying de-rating factors to the signal paths. Thus, a signal path that was validated during GLS may violate setup and hold times in STA and be identified as a critical path.
Signal paths identified as critical paths during STA are analyzed to identify the validity of the identified critical paths, which is time consuming. If the netlist does not meet the timing requirements, the steps of the IC design process are re-performed. Thus, the whole process consumes many engineering hours. Thus, it is very beneficial to verify the timing constraint file at an early stage and also to generate an SDF file that includes on-chip violation delay information.
One known technique to hasten the GLS is to generate a partial timing model of the IC design. The partial timing model includes timing information of the circuit elements of the IC design some, but not all, signal paths in the IC design, and the other circuit elements of the netlist are delay annotated with a zero delay value. The EDA tool performs the GLS using the partial timing model. Although this technique helps in reducing the time required for performing GLS, it fails to perform a complete verification of the timing constraints for the IC design.
Therefore, it would be advantageous to have a system and method that verifies timing constraints of an IC design represented by a netlist at a very early stage of the IC design.